Verilog — 119 Operations for AI Agents

This page is the canonical reference an AI coding agent uses to refactor, query, and analyze Verilog code through the act MCP server. 119 operations available: 45 refactor, 18 query, 42 analysis, 14 verification. Each operation is callable from Claude Code, Cursor, Codex, OpenCode, or any MCP-compatible agent host. Click any operation for a stable anchor link suitable for citation.

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18Query

45Refactor

42Analysis

14Verify

Query

18 query tools, the same on every supported language. Descriptions live in the shared reference: /docs/query-tools.

callers control_flow data_flow definition diagnostics effect_closure effect_summary fix_auto get_type graph import_organize interface mutations references repo_outline skeleton symbols symbols_batch

Refactor

Operation	Description
`add-bit-width-fix`	Add explicit bit width [N-1:0] to a wire/reg declaration
`add-clock-domain`	Add clock signal to always block (convert to always @(posedge clk))
`add-default-case`	Add a default case to an incomplete case statement
`add-function-declaration`	Declare a function skeleton inside a module
`add-intermediate-signal`	Introduce a named intermediate signal for a complex expression
`add-module-instantiation`	Create an instance of a module with port connections
`add-parameter`	Add a parameter to a module
`add-pipeline-register`	Insert a pipeline register between two logic stages
`add-port-connection`	Add a missing port connection to a module instantiation
`add-reg-declaration`	Add a reg declaration for an assignment target
`add-reset-logic`	Add reset signal handling to a sequential always block
`add-sensitivity-list`	Add missing signals to always block sensitivity list
`add-task-declaration`	Declare a task skeleton inside a module
`add-wire-declaration`	Add a wire declaration for an undefined signal
`convert-always-to-continuous`	Convert a simple combinational always block to a continuous assign statement
`convert-continuous-to-always`	Convert a continuous assign statement to an always @(*) block
`convert-for-loop-to-generate`	Convert a for loop to a generate block
`convert-generate-to-loop`	Convert a generate block to a for loop
`convert-mux-to-case`	Convert a ternary mux expression to a case statement
`convert-reg-to-wire`	Change a reg declaration to wire
`convert-to-blocking`	Convert non-blocking <= assignments to blocking = in a combinational always block
`convert-to-nonblocking`	Convert blocking = assignments to non-blocking <= in a sequential always block
`convert-wire-to-reg`	Change a wire declaration to reg
`extract-always-block`	Extract procedural logic from an always block into a new always block
`extract-function`	Extract repeated logic into a Verilog function
`extract-module`	Extract a range of lines into a new module
`extract-task-from-always`	Extract procedural logic from an always block into a task
`extract_function`	Extract a code selection into a new function — automatically infers parameters, return types, and inserts the call site. Use instead of manually cutting/pasting code. Works without LSP; LSP improves type inference. Params: file (string), new_name (string), start_line (u32), start_column (u32), end_line (u32), end_column (u32) [, preview (bool), receipt (bool)]
`extract_variable`	Extract an expression into a named variable — inserts the declaration and replaces the expression with the variable name. Works without LSP. Params: file (string), new_name (string), start_line (u32), start_column (u32), end_line (u32), end_column (u32) [, preview (bool)]
`generate-module-stub`	Generate a module skeleton with header and endmodule
`generate-testbench`	Generate a testbench skeleton for a module
`inline`	Inline a variable, function, or method — replace every usage with its definition body, then remove the original. The inverse of extract. Works without LSP (single-file); LSP enables cross-file inlining. Params: file (string), symbol (string) [, line (u32), preview (bool), receipt (bool)]
`inline-parameter`	Inline a parameter value, replacing all references with its value
`insert_body`	Replace a function's implementation body with new code. AST-validated — rejects if the result has parse errors, so you can't accidentally break syntax. Use instead of manual text editing for function rewrites. Params: file (string), symbol (string), code (string) [, commit (bool)]
`move_symbol`	Move a function, class, or type to a different file and automatically update all imports across the codebase. Use instead of manually cut/paste + fixing imports. Works without LSP (single-file); LSP enables cross-file import updates. Params: file (string), symbol (string), destination (string) [, preview (bool), receipt (bool)]
`recipe_run`	Run a codemod recipe: declarative match → transform → optional verify across modeled grammars. Preview lists matches; apply writes with optional E7 receipts and all-or-nothing rollback. Returns a per-site report.
`remove-unused-function`	Remove an unused function declaration
`remove-unused-parameter`	Remove an unused parameter declaration
`remove-unused-port`	Remove an unused port from the module declaration
`remove-unused-signal`	Remove an unused wire, reg, or variable declaration
`remove-unused-task`	Remove an unused task declaration
`rename`	Rename a symbol and automatically update ALL references across the codebase. Safer and faster than find-and-replace — AST-aware, won't rename strings or comments. Works without LSP (single-file); LSP enables cross-file renames. Params: file (string), old_name (string), new_name (string) [, line (u32), column (u32), preview (bool), receipt (bool)]
`rename-identifier`	Rename a signal, port, or identifier across all references
`rename-module`	Rename a module and all its instantiation references
`rename-parameter`	Rename a parameter across all references

Analysis

42 analysis tools, the same on every supported language. Descriptions live in the shared reference: /docs/analysis-tools.

analyze_api_diff analyze_chokepoints analyze_clones analyze_clusters analyze_cohesion analyze_conformance analyze_coupling analyze_cycle_risk analyze_cycles analyze_dead_code analyze_depth analyze_entry_points analyze_export analyze_extraction analyze_fan_balance analyze_features analyze_hotspots analyze_impact analyze_inconsistencies analyze_inheritance analyze_interface_bloat analyze_interfaces analyze_layers analyze_orphan_types analyze_patterns analyze_platform_deps analyze_readiness analyze_roles analyze_seams analyze_stability analyze_surface analyze_test_gaps analyze_thickness analyze_type_completeness churn_hotspots co_change_clusters coverage_overlay ownership_map profile_overlay simulate split_module trace_overlay

Verify

14 verify tools, the same on every supported language. Descriptions live in the shared reference: /docs/verification.

bisect_regression gate generate_test_harness scan secret_surface summarize_pr taint_flow unsafe_surface verify_behavioral_equivalence verify_contract_preserved verify_diff_semantics verify_port_parity verify_side_effects verify_test_impact

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