FIRRTL — 121 Operations for AI Agents

FIRRTL is the hardware IR between Chisel designs and silicon. act101 reads circuit modules and ports as structure, so agents inspect generated hardware without drowning in lowered output.

This page is the canonical reference an AI coding agent uses to refactor, query, and analyze FIRRTL code through the act MCP server. 121 operations available: 47 refactor, 18 query, 42 analysis, 14 verification. Each operation is callable from Claude Code, Cursor, Codex, OpenCode, or any MCP-compatible agent host. Click any operation for a stable anchor link suitable for citation.

Premium language. Operations on FIRRTL require an Elite license or above. See pricing.

18Query

47Refactor

42Analysis

14Verify

Query

18 query tools, the same on every supported language. Descriptions live in the shared reference: /docs/query-tools.

callers control_flow data_flow definition diagnostics effect_closure effect_summary fix_auto get_type graph import_organize interface mutations references repo_outline skeleton symbols symbols_batch

Refactor

Operation	Description
`add-port`	Add a new port to a FIRRTL module
`add-reset-logic`	Add explicit reset behavior to a FIRRTL register that lacks a reset block
`add-wire`	Add a new wire declaration to a FIRRTL module
`change-port-direction`	Flip a FIRRTL port's direction between input and output
`change-reset-type`	Convert a FIRRTL register's reset between synchronous and asynchronous
`convert-bundle-to-ports`	Replace a bundle-typed port with one scalar port per bundle field
`convert-mem-to-reg-array`	Replace a memory (mem/smem/cmem) declaration with a register of vector type
`convert-mux-to-when`	Expand a FIRRTL mux-driven connection into an explicit when/else pair
`convert-reg-array-to-mem`	Replace a vector-typed register declaration with a mem declaration
`convert-to-register`	Convert a FIRRTL wire into a clocked register with reset
`convert-to-wire`	Convert a FIRRTL register or node into a wire declaration
`convert-when-to-mux`	Collapse a FIRRTL when/else pair driving one signal into a mux connection
`create-hierarchy`	Extract a FIRRTL statement range into a new child module + instance
`extract-module`	Extract a contiguous statement range into a new FIRRTL module with inferred boundary ports
`extract-node`	Extract a sub-expression into a named FIRRTL node declaration
`extract_function`	Extract a code selection into a new function — automatically infers parameters, return types, and inserts the call site. Use instead of manually cutting/pasting code. Works without LSP; LSP improves type inference. Params: file (string), new_name (string), start_line (u32), start_column (u32), end_line (u32), end_column (u32) [, preview (bool), receipt (bool)]
`extract_variable`	Extract an expression into a named variable — inserts the declaration and replaces the expression with the variable name. Works without LSP. Params: file (string), new_name (string), start_line (u32), start_column (u32), end_line (u32), end_column (u32) [, preview (bool)]
`fix-combinational-loop`	Break a direct combinational self-loop by inserting a register
`fix-direction-mismatch`	Correct the connection direction for an instantiation port
`fix-missing-default`	Insert a default `is invalid` driver for an undriven wire or output
`fix-unconnected-port`	Insert a default connection for a dangling instantiation port
`fix-width-mismatch`	Fix a width mismatch in a FIRRTL connection by inserting pad() or bits()
`flatten-hierarchy`	Inline all instances in a FIRRTL module, flattening its hierarchy
`gen-arbiter`	Generate a priority or round-robin arbiter module over N requesters
`gen-counter-module`	Generate a loadable counter module and append it to the circuit
`gen-fifo-module`	Generate a synchronous FIFO module with full/empty flags
`gen-memory-interface`	Generate a memory read/write port interface module
`gen-module-scaffold`	Generate a new skeleton FIRRTL module and append it to the circuit
`gen-pipeline-stage`	Generate a parameterized pipeline register stage module
`gen-shift-register`	Generate a shift-register module and append it to the circuit
`gen-testbench-scaffold`	Generate a testbench module that instantiates and drives a DUT module
`inline`	Inline a variable, function, or method — replace every usage with its definition body, then remove the original. The inverse of extract. Works without LSP (single-file); LSP enables cross-file inlining. Params: file (string), symbol (string) [, line (u32), preview (bool), receipt (bool)]
`inline-module`	Inline a single-use FIRRTL module instance body into its parent
`inline-node`	Inline a single-use FIRRTL node by replacing its use with the RHS expression and deleting the declaration
`insert_body`	Replace a function's implementation body with new code. AST-validated — rejects if the result has parse errors, so you can't accidentally break syntax. Use instead of manual text editing for function rewrites. Params: file (string), symbol (string), code (string) [, commit (bool)]
`merge-adjacent-when`	Merge two adjacent FIRRTL when blocks with identical conditions into one
`move_symbol`	Move a function, class, or type to a different file and automatically update all imports across the codebase. Use instead of manually cut/paste + fixing imports. Works without LSP (single-file); LSP enables cross-file import updates. Params: file (string), symbol (string), destination (string) [, preview (bool), receipt (bool)]
`recipe_run`	Run a codemod recipe: declarative match → transform → optional verify across modeled grammars. Preview lists matches; apply writes with optional E7 receipts and all-or-nothing rollback. Returns a per-site report.
`remove-port`	Remove an unreferenced port from a FIRRTL module
`remove-wire`	Remove an unreferenced wire declaration from a FIRRTL module
`rename`	Rename a symbol and automatically update ALL references across the codebase. Safer and faster than find-and-replace — AST-aware, won't rename strings or comments. Works without LSP (single-file); LSP enables cross-file renames. Params: file (string), old_name (string), new_name (string) [, line (u32), column (u32), preview (bool), receipt (bool)]
`rename-module`	Rename a FIRRTL module and update all instantiation references
`rename-node`	Rename a FIRRTL node (intermediate value) within its declaring module
`rename-port`	Rename a FIRRTL port within its module and update cross-module instance references
`rename-register`	Rename a FIRRTL register within its declaring module
`rename-wire`	Rename a FIRRTL wire within its declaring module
`split-when-block`	Split a multi-statement FIRRTL when block into separate same-condition when blocks

Analysis

42 analysis tools, the same on every supported language. Descriptions live in the shared reference: /docs/analysis-tools.

analyze_api_diff analyze_chokepoints analyze_clones analyze_clusters analyze_cohesion analyze_conformance analyze_coupling analyze_cycle_risk analyze_cycles analyze_dead_code analyze_depth analyze_entry_points analyze_export analyze_extraction analyze_fan_balance analyze_features analyze_hotspots analyze_impact analyze_inconsistencies analyze_inheritance analyze_interface_bloat analyze_interfaces analyze_layers analyze_orphan_types analyze_patterns analyze_platform_deps analyze_readiness analyze_roles analyze_seams analyze_stability analyze_surface analyze_test_gaps analyze_thickness analyze_type_completeness churn_hotspots co_change_clusters coverage_overlay ownership_map profile_overlay simulate split_module trace_overlay

Verify

14 verify tools, the same on every supported language. Descriptions live in the shared reference: /docs/verification.

bisect_regression gate generate_test_harness scan secret_surface summarize_pr taint_flow unsafe_surface verify_behavioral_equivalence verify_contract_preserved verify_diff_semantics verify_port_parity verify_side_effects verify_test_impact

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